The present invention relates to the field of Integrated Circuit (IC) design using Electronic Design Automation (EDA) tools, and in particular, to a method and system for verifying level shifters in a multi-voltage IC design.
IC design is now carried out using special Computer Aided Design (CAD) tools, sometimes known as EDA tools. These tools assist an IC designer to produce complex integrated circuitry, such as System on Chip (SoC) ICs, by not only assisting in the conversion of logical design parameters (from varying degrees of abstraction) into physical layout data for use in producing the semiconductor production masks, and the like, but also to aid in the testing of designs for correct operation and suitability for the chosen manufacturing process(es).
Many IC designs today make use of multiple (different) voltage domains, where each domain may be supplied by a power supply voltage optimised for its task or structure. IC designers may particularly use such multiple voltage domain architectures because they allow IC designers to implement large, complex SoCs that consume the less power, while delivering the required performance and functionality.
In digital circuits in general, a logic level is one of a finite number of states that a signal can have and is usually represented by a voltage difference between the respective signal and some common reference voltage point, such as ground (0 volts). The range of voltage levels that represents each state may depend on the logic family being used, but a typical example is the use of binary logic levels, such as “1” and “0”, where, for example, “0”indicates a voltage at or near ground (0V), and “1” indicates a voltage at or near the maximum power supply voltage of the IC (or portion thereof)—e.g. 1.2V, 3.3V, 5V, etc., where the power supply voltage for the IC is 1.2V, 3.3V, and 5V respectively.
As voltages increase (or IC minimum dimensions decrease), means to avoid transistor breakdown (i.e. inbuilt protection) may need to be employed in circuits operating at the higher voltages. For example, in ICs using Metal on Silicon (MOS) type transistor technology, this protection may take the form of increasing, e.g. doubling, the gate oxide for the high voltage transistors, producing so called Double Gate Oxide (DGO) type cells.
When an IC design includes multiple voltage domains, a level shifter is used to shift a signal voltage (e.g. an output voltage) of a first power supply voltage domain to a suitable signal voltage (e.g. an input voltage) of a second power supply voltage domain or vice-versa. As such, a level shift function within an IC design may comprise, for example, shifting a logical “1” at 1.2V to a logical “1” at 3.3V (or a logical “1” at 1.2V to a logical “1” at 5V, or vice-versa), and the like. That is to say, a level shift operation may comprise either shifting the voltage from a low(er) voltage to a high(er) voltage or from a high(er) voltage to a low(er) voltage. If a level shifter is missing between two voltage domains, there will be an invalid power domain crossing. Therefore, multiple power domain IC designs need to be verified extensively for possible violations of signals not being level shifted when crossing domains.